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SYCLops: A SYCL Specific LLVM to MLIR Converter

Link to source code

Presented at the International Workshop on OpenCL (IWOCL) & SYCLCon’22 conference. IWOCL

The LLVM Project is an open-source compiler framework that takes source files, written in a supported programming language (like C++), optimizes it, and then lowers it to binary. LLVM uses an intermediate representation of the code called LLVMIR. LLVMIR is low level, so it can be lowered to a target binary, however high enough level to perform optimizations for CPU targets.

Multi-Level Intermediate Representation, or MLIR, is a relatively new framework based off the LLVM project. It mixes different levels of abstraction within the same source file, allowing for higher level optimizations, including affine analysis.

SYCL is a C++ abstraction layer for heterogeneous applications (code to be run on a host CPU and some other device, like hardware accelerators). oneAPI is an implementation of SYCL, based off LLVM, that we chose to work with. oneAPI uses LLVMIR for its device code, however we feel that MLIR would provide better optimizations for accelerator targets.

Thus, we introduce SYCLops, which is a converter capable of taking the device code from oneAPI’s SYCL implementation and converting it into MLIR. The device compiler can then perform optimizations within MLIR’s Affine dialect before lowering it back to LLVM for further optimizations and lowering.